1. Field of the Invention
The invention relates to memory module architectures and in particular relates to an enhanced memory module configuration to provide additional flexibility in memory module applications in conjunction with PowerPC and other system applications.
2. Discussion of Related Art
Present-day computing systems often utilize standardized memory modules to add memory capacity to a system. A memory module is generally comprised of a number of memory chips mounted on a printed circuit card adapted for insertion into a standard carrier or socket connector. The module is easily added or removed from a system to permit flexible configuration of memory capacity. The module and socket adhere to a standardized pin assignment for exchange of signals between a system bus and the memory chips. Signals are routed from the carrier connector to the memory chips in accordance with the particular standard used for the module and the particular memory chips selected by the memory module manufacturer.
A number of standards are defined for such modules. Exemplary of one such standard is a so-called 144-pin Small Outline DIMM module (also referred to as xe2x80x9cSO-DIMMxe2x80x9d) as defined by the JEDEC JESD21-C standard specification (available online at www.jedec.org). The 144-pin SO-DIMM provides a convenient, compact design for use in space-constrained applications such as portable computing devices or embedded systems. The module is a small printed circuit card with memory devices mounted thereon and one edge that provides electrical connectivity of up to 144 signals when the module is inserted into a mated connector on the main system board (i.e., the system motherboard). The printed circuit card signal traces connect standard signals assigned to the 144 pins of the module""s edge connector to appropriate pins of the memory chips mounted thereon. A memory controller on the system board exchanges these standard memory control signals with the module through the mated connector.
In particular, the 144-pin standard module provides for memory chips to be mounted on one or both physical sides of the printed circuit board. A select signal is typically applied to the module by a CPU or memory controller to select the memory chips on one or the other side of the memory module for exchange of data and control signals. This select signal is often referred to as a xe2x80x9crow selectxe2x80x9d signal in regards to the 144-pin standard configuration. When the xe2x80x9cfrontxe2x80x9d side is selected by the memory controller, only those chips respond to the exchange of signals with the system board. Similarly, when the xe2x80x9cbackxe2x80x9d side is selected, only those memory chips respond to the memory controller signals.
Most memory modules and carriers define signal connections for standard DRAM memory devices (dynamic random access memory) mounted on the module. Such signal definitions include signals common to most DRAM devices including, in particular, SDRAMs (synchronous DRAM devices). Other forms of memory, in particular asynchronous memories, are not generally accommodated by the standard signal paths provided for on the standard DIMM memory module. For example, present standard DIMM modules such as the 144-pin SO-DIMM do not support so-called Flash memory devices. Neither are static RAMs (SRAM devices) generally supported by such standard DIMM modules.
This presents a particular problem to embedded applications where a wide variety of memory devices are often applied to resolve special problems in particular applications. For example, the non-volatile nature of Flash memory devices makes them particularly useful in many embedded applications for storage of computer program instructions while a standard SDRAM may be used for storage and retrieval of program data. Since no single standard memory module supports such a variety of memory devices, it is often necessary to design embedded applications for multiple memory module architectures and associated busses and/or to redesign the system as the memory requirements change or new memory components become available. For example, it is common in many such embedded applications to design a first memory bus for exchange of signals with synchronous memory components (i.e., SDRAMs) and a separate slower memory bus for asynchronous devices such as Flash or static RAMs. This added complexity adds cost and size to the design and complicates portability of a system design to multiple applications that may have different needs for memory configuration.
Furthermore, it is a problem for many such memory module designs to be used in embedded applications where there is significant vibration or mechanical shock. Standard DIMM modules insert into a mated socket at one edge. Some DIMM modules are designed to latch or lock on two other sides of the module. However, the edge opposing the socket is often unsupported and may lead to failures in applications of high vibration and mechanical shock. In particular it has been found that under certain common vibrational modes, the SO-DIMM module may twist about a pivot point at the key in the DIMM socket. Sufficient twisting due to such vibration can lead to unacceptable, premature DIMM module failure.
It is evident from the above discussion that a need exists for an improved memory module design that permits a wider variety of memory device types to be used in a standard DIMM socket on a common bus. It is further evident that a need exists for an improved mechanical design for a memory module that better withstands high vibration environments or environments that may entail significant mechanical shock.
The present invention solves the above and other problems, thereby advancing the state of the useful arts, by providing a modified memory module design that accommodates a wider variety of memory devices. In particular, the modified memory module architecture of the present invention redefines a number of standard signals to permit utilization of Flash and static memory components in a DIMM module while maintaining backward compatibility to standard DRAM and SDRAM DIMM modules. Still more specifically in one exemplary preferred embodiment, the present invention preferably utilizes row select signals (xe2x80x9cCS(0:1)xe2x80x9d) of a standard 144-pin SO-DIMM module to provide requisite select and control signals for Flash and static memory devices.
Still more specifically, where a memory controller is capable of multiplexing both synchronous and asynchronous memory device accesses over the same signal paths, the present invention permits use of Flash and other special memory modules that are physically compatible with SO-DIMM configurations in conjunction with typical SDRAM (or other DRAM) SO-DIMM modules over the same multiplexed memory controller bus signals. For example, the Motorola family of embedded PowerPC microcomputers (MPC824x and others) includes such a memory controllerxe2x80x94specifically the MPC107 memory controller. The MPC106 or MPC107 memory controller device provides such a memory controller feature and is integrated into the MPC824x chip die and available as a separate integrated circuit component. Systems using the MPC106 or MPC107 memory controller as a separate component may also benefit from the present invention. Further, other similarly featured memory controllers are commercially available and systems using such similarly featured memory controller may beneficially apply the features of the present invention.
In one particularly useful embodiment, the signals of a JEDEC JESD21-C 144-pin SO-DIMM standard memory module are modified to enable support of Flash and SRAM memory devices on the modified standard DIMM module. In particular, the chip select (row select) signals are modified to provide the requisite selection of Flash and SRAM memory components in addition to standard SDRAM (or DRAM) memory components. Setting of jumpers on the system board preferably indicate the presence of such additional memory device types in the SO-DIMM sockets of the system and adapt the signal exchange with a memory controller to conform to the signaling requirements of the special module. A single bus structure supports both synchronous and asynchronous memory device signals and couples the memory controller to multiple SO-DIMM sockets. Each DIMM socket may be populated with a Flash or SRAM special memory module or with a standard SDRAM or DRAM memory module. The design may then be easily ported to other applications requiring a different compliment of memory device types.
In this first exemplary preferred embodiment, a variety of memory configurations are achievable. In this first exemplary preferred embodiment, the system utilizes a DIMM module similar to that defines as the 144-pin SO-DIMM standard referenced above. In such memory modules, the module may be populated on one or both sides of the module printed circuit card with memory devices. All memory devices on one side typically respond to the same select signal. The select signal is usually referred to as a xe2x80x9crow selectxe2x80x9d as noted above. As used herein, the terms xe2x80x9crowxe2x80x9d and xe2x80x9csidexe2x80x9d are used synonymously with respect to such SO-DIMM modules. Those skilled in the art will note however that it is not required that all memory devices on one side of a module respond to a single select signal. Rather, in accordance with the module standard, the physical place of the memory devices on the module is irrelevant with respect to the select signals. Use of the terms xe2x80x9crowxe2x80x9d and xe2x80x9csidexe2x80x9d as essentially synonymous is therefore not intended to limit the invention to a particular physical layout of memory modules. Rather, the terms are both used to broadly refer to a first subset of memory devices on a module that respond to a first row select signal and a second subset of memory devices that respond to a second row select signal.
With two DIMM sockets in an exemplary system configuration, each socket may be populated with a standard SDRAM SO-DIMM where the DIMM is limited to single row configurations (i.e., SDRAM memory devices responding to only one row select of the module). Alternatively, only one DIMM socket may be populated with a double-row SO-DIMM module. The double-row DIMM may provide SDRAM devices on both rows, SDRAM on one row and Flash or other asynchronous devices on the other. In yet another alternative, a first single row DIMM may provide SDRAM memory devices and a second single row DIMM may provide Flash or other asynchronous memory devices. Jumper configurations on the system printed circuit board can then be used to route the row select signals as appropriate for the particular application.
In an alternative embodiment of the present invention, use of the serial presence detect (xe2x80x9cSPDxe2x80x9d) signaling standard of DIMMs provides the required identity of the special modules supporting the extended range of memory device types. The SPD feature of memory modules provides for a simple serial interface (usually I2C protocol compliant) to return to the system certain identification and configuration information regarding the memory module. The memory controller of the system is then programmed to adapt its signaling as required for the sensed memory configuration. An application specific integrated circuit (ASIC) could be used in addition to a memory controller or in place of a memory controller to provide desired address processing. In general, a system CPU would preferably sense the configuration of memory modules in the sockets by reading and decoding the SPD information and program the memory controller and/or ASIC device to provide appropriate address decoding and timing according to the specific compliment of memory modules found in the system.
Another aspect of the present invention provides a support structure for the DIMM edge opposite the connector edge to enhance the module""s resistance to vibration and mechanical shock. The present invention provides a support structure associated with the edge of a SIMM module opposite the connector edge of the DIMM. The support structure prevents a module inserted in the SO-DIMM socket from rotating or twisting within the socket connector. In particular, the present invention preferably prevents the module from twisting about an axis centered at the key of the module socket.
In one exemplary preferred embodiment representing the best presently known mode of practicing the invention, the module is adapted with holes at the corners, each overlaying a swaged extension nut or standoff on the motherboard or system board. The holes and associated nut or standoff are preferably positioned at the corners of the module opposite the connector edge of the module. The module is inserted in the mated connector and preferably secured with screws or other fasteners to the standoff or extension nut to immobilize the module and prevent undesired twisting of the module in the socket.
A first feature of the invention provides for a memory module comprising: a printed circuit assembly having connector pads at one edge of the assembly; and a plurality of memory devices mounted on the assembly and electrically coupled to the connector pads such that the printed circuit assembly is adapted to support both synchronous and asynchronous types of the memory devices.
Another aspect further provides that each of the plurality of memory devices is a synchronous dynamic random access memory device.
Another aspect further provides that each of the plurality of memory devices is a synchronous Flash memory device.
Another aspect further provides that each of the plurality of memory devices is an asynchronous Flash memory device.
Another aspect further provides that each of the plurality of memory devices is an asynchronous static random access memory device.
Another aspect further provides that each of the plurality of memory devices is an asynchronous fast static random access memory device.
Another aspect further provides that each of the plurality of memory devices is an asynchronous low power static random access memory device.
Another aspect further provides that the connector pads include: a first select signal connector pad that selects a first subset of memory devices mounted on the module when a signal is applied thereto such that the first subset of memory devices are synchronous memory devices; and a second select signal connector pad that selects a second subset of memory devices mounted on the module when a signal is applied thereto such that the second subset of memory devices are asynchronous memory devices.
Another aspect further provides that the connector pads include: a first select signal connector pad that selects a first subset of memory devices mounted on the module when a signal is applied thereto such that the first subset of memory devices are synchronous dynamic random access memory devices; and a second select signal connector pad that selects a second subset of memory devices mounted on the module when a signal is applied thereto such that the second subset of memory devices are synchronous Flash memory devices.
A second feature of the invention provides for a system comprising: a system board; a memory bus adapted for exchanging signals between a memory controller and both synchronous and asynchronous memory devices; a memory controller on the system board coupled to the memory bus such that the memory controller is capable of generating signals for control of both synchronous and asynchronous memory devices and such that the memory controller is capable of multiplexing the signals on the memory bus; a first socket connector on the system board for receiving a first memory module such that the first socket connector is coupled to the memory controller through the memory bus; and a first memory module inserted in the first socket connector and electrically coupled to the memory controller such that the first memory module includes a plurality of synchronous or asynchronous memory devices.
Another aspect further provides for a jumper on the system board for configuring signals exchanged between the memory controller and the first memory module in accordance with the type of memory devices on the first memory module.
Another aspect further provides that the first memory module provides serial presence detect information used in conjunction with the memory controller to identify the type of memory devices included on the first memory module.
Another aspect provides for a second socket connector on the system board for receiving a second memory module such that the second socket connector is coupled to the memory controller through the memory bus; and a second memory module inserted in the second socket connector and electrically coupled to the memory controller such that the second memory module includes a plurality of synchronous or asynchronous memory devices.
Another aspect further provides for a jumper on the system board for configuring signals exchanged between the memory controller and the second memory module in accordance with the type of memory devices on the first memory module and on the second memory module.
Another aspect further provides that the first memory module provides serial presence detect information used in conjunction with the memory controller to identify the type of memory devices included on the first memory module, and that the second memory module provides serial presence detect information used in conjunction with the memory controller to identify the type of memory devices included on the second memory module.
A third feature of the invention provides for a system comprising: a system board; a socket connector on the system board for receiving a memory module such that the socket connector includes a key; a memory module having a connector edge inserted in the socket connector and having an opposing edge opposite the connector edge such that the memory module has a notch mated to the key when the memory module is inserted in the socket connector; and a memory module retainer adapted to substantially immobilize the opposing edge with respect to rotation about the key.
Another aspect further provides that the memory module retainer comprises: a nut affixed to the system board; a hole in the memory module along the opposing edge and aligned with the nut; and a screw inserted through the hole into the nut to substantially immobilize the opposing edge with respect to rotation about the key.
Another aspect provides that the nut is a swaged extension nut.
Another aspect provides that the memory module retainer comprises: a half card-cage affixed to the system board such that the half card-cage includes a channel for receiving the opposing edge of the memory module to substantially immobilize the opposing edge with respect to rotation about the key.
Another aspect provides that the memory module retainer comprises: a standoff pin affixed to the system board; a hole in the memory module along the opposing edge and aligned with the pin such that the standoff pin extends through the hole and locks when the memory module is completed inserted in the socket connector to substantially immobilize the opposing edge with respect to rotation about the key.
Another aspect provides that the memory module retainer comprises: a standoff pin affixed to the socket connector, a hole in the memory module aligned with the standoff pin such that the standoff pin extends through the hole and when the memory module is completed inserted in the socket connector to substantially immobilize the opposing edge with respect to rotation about the key.